![]() ![]() In this example, the FSBL is targeted for APU Cortex™-A53Ĭore 0. The FSBL can be run from either APU A53_0, RPU R5_0, or RPU R5_lockstep. Unit loads the first stage boot loader (FSBL) into on-chip memory (OCM). At this stage, the configuration security ![]() In non-secure boot mode, the platform management unit (PMU) releases the reset of the configuration security unit, and enters the PMU server mode to monitor power. Design Example 1: Using GPIOs, Timers, and Interrupts covers the boot image which will include the PS partitions used in this chapter and a bitstream targeted for the PL fabric. This chapter makes use of a processing system block. The Bootgen GUI facilitates the creation of the BIF input file. It can be used to program non-volatile memories such as QSPI and SD cards. It can also create cryptographic keys.įunctionally, Bootgen uses a BIF (Bootgen image format) file as an input, and generates a single file image in binary BIN or MCS format. It allows you to specify security options. The principle function of the Create Boot Image wizard or Bootgen is to integrate the partitions (hardware-bitstreamĪnd software) in the proper format. To create a boot image, you can either use the Create Boot Image wizard in the Vitis IDE, or the BootgenĬommand line tool (the Create Boot Image wizard calls the Bootgen tool as well). The PS, this chapter explains how these blocks can be loaded as a part of a bigger system. While previous sections focused only on creating software blocks for each processing unit in Note: For more information on RPU lockstep, see the Zynq UltraScale+ Device Technical Reference Manual ( UG1085).
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